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Compilation issue with aie++

Status: Open.

#236 In triSYCL/sycl;

· keryell opened on Aug 17, 2023

xrt_piEventGetProfilingInfo not implemented

bugSomething isn't workingSomething isn't working

Status: Open.

#224 In triSYCL/sycl;

· keryell opened on Apr 7, 2023

Build issue with RHEL8

bugSomething isn't workingSomething isn't working

Status: Open.

#192 In triSYCL/sycl;

· jyoung3131 opened on Jul 15, 2022

There are still some xocc and XOCC in sycl/test/lit.cfg.py

Status: Open.

#188 In triSYCL/sycl;

· keryell opened on Jun 21, 2022

Implement USM support for XRT plugin

enhancementNew feature or requestNew feature or request

Status: Open.

#181 In triSYCL/sycl;

· keryell opened on May 13, 2022

Is barrier in kernel supported or going to be supported?

enhancementNew feature or requestNew feature or request

Status: Open.

#180 In triSYCL/sycl;

· fxzjshm opened on May 4, 2022

Do not generate DDR bank by default if there is no DDR but HBM

bugSomething isn't workingSomething isn't working

Status: Open.

#176 In triSYCL/sycl;

· keryell opened on Apr 29, 2022

fpga_hls_hw_emu fails in vpl step

bugSomething isn't workingSomething isn't working

Status: Open.

#168 In triSYCL/sycl;

· j-stephan opened on Mar 2, 2022

Simplify difference in clang/test/CodeGenSYCL/loop_unroll.cpp

Status: Open.

#159 In triSYCL/sycl;

· keryell opened on Jan 27, 2022

Handling also sycl::ext::xilinx

enhancementNew feature or requestNew feature or request

Status: Open.

#157 In triSYCL/sycl;

· keryell opened on Jan 27, 2022

Adding more small examples from old triSYCL to compare with HLS

Status: Open.

#149 In triSYCL/sycl;

· keryell opened on Oct 23, 2021

xilinx::pipeline_kernel not compiling

Status: Open.

#148 In triSYCL/sycl;

· keryell opened on Oct 23, 2021