Hardwired bits in TDATA1

[jrahmeh]

The spec says that the vu/vs bits of mcontrol6 should be hardwired to 0 if virtualization is not supported. Same for icount.
The vu/vs bits are in positions 23/24 for mcontrol6 and 25/26 for icount.

How should this work on an implementation that supports multiple types (mcontrol6 and icount) for the same trigger?
When the trigger type is mcontrol6 bits 23/24 are hardwired to 0. When the type is icount, bits 25/26 are hardwired to zero.
But bit 25 is hit1 in mcontrol6, it cannot be hardwired to 0.

Does this imply that each trigger must have a fixed type?

[pdonahue-ventana]

I interpret this as meaning that the only legal value for WARL purposes is 0. So if you write type=icount then no matter what you write into bit 25/26, you're going to read back 0. If you write type=mcontrol6 then no matter what you write into bit 23/24, you're going to read back 0.

It could probably be written better. The word "hardwired" is used in many places and it should probably be "read-only zero" in some of those places (where positions don't change) and something like "the only legal WARL value is 0" in others.

[jrahmeh]

It would be nice if the spec also specified what the read value of tdata1 should be when the type is "disabled". If we write a 1 to bit 25 (hit1) when the type is mcontrol6, then change the type to "disabled", what should the read value pf bit 25 be? Is it the read-only-zero associated with the icount type? Or is it the 1 we wrote when the type was mcontrol6? Or, should all the bits of the data filed of tdata1 be read-only-zero when the type is "disabled".