SIGILL on some XEON CPU caused by prebuilt bin in Docker container #470
Description
Description
The Ursa process finishes with exit code 132 (interrupted by signal 4: SIGILL) on some XEON CPUs.
A Docker image is provided, prebuilt on an x86_64 DigitalOcean Intel vCPU machine, which is not supported by some Intel processors that VPS providers might supply.
A few examples of CPU are:
- Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz
Here are a few examples of VPS provider's client VPS where this was observed:
As a temporary solution, the user is asked to build the image instead of accepting the recommended "latest" or "nightly". This means that cargo build enables or disables some CPU features by considering the native CPU in which the build is launched.
Environment
- We're providing a prebuilt Docker image, cargo built by a GitHub workflow
- On the prebuilt binary, run as a Docker container
- The CI runs Ubuntu's latest
Demo
As discussed and observed in: https://discord.com/channels/965698989464887386/1047823650541277194/1090335532669735053
Another user:
https://discord.com/channels/965698989464887386/1047823650541277194/1090966733130580008
For clarity, this has nothing to do with Docker. Here we see a binary built natively DO Intel Ubuntu latest x86_64, attempt run on the XEON E5 VPS:
Notes
Debugging details
Starting program: /usr/local/bin/ursa
warning: Error disabling address space randomization: Operation not permitted
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
[New Thread 0x7fb8b1615700 (LWP 627)]
[New Thread 0x7fb8b1414700 (LWP 628)]
[New Thread 0x7fb8b120d700 (LWP 629)]
[New Thread 0x7fb8b1009700 (LWP 630)]
2023-03-30T18:47:59.665085Z INFO ursa::config: Loading config from: "/root/.ursa/config.toml"
at crates/ursa/src/config.rs:36
2023-03-30T18:47:59.679817Z INFO ursa::ursa::identity: Loaded identity `default` (12D3KooWSUuPHmNLj3z9TxjdHjHpEdb1Pr49cWbogdC1M6ZjH2r1)
at crates/ursa/src/ursa/identity.rs:155
2023-03-30T18:47:59.680409Z INFO ursa_consensus::keys: Creating '"/root/.ursa/keystore/consensus/primary.key"' because it doesn't exists.
at crates/ursa-consensus/src/keys.rs:43
Thread 1 "ursa" received signal SIGILL, Illegal instruction.
0x000056316b498a2f in ?? ()
Asssembly
multi-thre Thread 0x7fce3fdb63 In: L?? PC: 0x5573c33eea2f
┌────────────────────────────────────────────────────────────────────────┐
│ >0x5573c33eea2f mulx %r14,%rax,%r11 │
│ 0x5573c33eea34 call 0x5573c33eeae0 │
│ 0x5573c33eea39 mov 0x8(%rsp),%r15 │
│ 0x5573c33eea3e mov 0x10(%rsp),%r14 │
│ 0x5573c33eea43 mov 0x18(%rsp),%r13 │
│ 0x5573c33eea48 mov 0x20(%rsp),%r12 │
│ 0x5573c33eea4d mov 0x28(%rsp),%rbx │
│ 0x5573c33eea52 mov 0x30(%rsp),%rbp │
│ 0x5573c33eea57 lea 0x38(%rsp),%rsp │
│ 0x5573c33eea5c repz ret │
│ 0x5573c33eea5e xchg %ax,%ax │
│ 0x5573c33eea60 endbr64 │
│ 0x5573c33eea64 push %rbp │
│ 0x5573c33eea65 push %rbx │
│ 0x5573c33eea66 push %r12 │
│ 0x5573c33eea68 push %r13 │
│ 0x5573c33eea6a push %r14 │
│ 0x5573c33eea6c push %r15 │
│ 0x5573c33eea6e sub $0x8,%rsp │
│ 0x5573c33eea72 mov %rsi,%rbx │
│ 0x5573c33eea75 mov %rcx,%r8 │
│ 0x5573c33eea78 mov %rdx,%rcx │
│ 0x5573c33eea7b mov (%rsi),%rdx │
│ 0x5573c33eea7e mov 0x8(%rsi),%r15 │
└────────────────────────────────────────────────────────────────────────┘
multi-thre Thread 0x7fce3fdb63 In: L?? PC: 0x5573c33eea2f
(gdb)
A mulx described here https://docs.oracle.com/cd/E37838_01/html/E61064/gnyak.html seems to be a CPU feature not available on older intel CPU such like the XEON E5 family above.
Obs: A cargo build with target x86_64-unknown-linux-gnu was attempted, but that seems to be used by default when no --target is specified. This was tested in a Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz VPS shared by a community member " LinKong| Sui Global" (on Discord).
Checklist
- I have ensured that my version is up-to-date
- I have ensured that my issue is reproducible
- I have ensured that my issue is not a duplicate
Activity